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cmos lsi ordering number : en 5580a 33098ha(ot)/22897ha(ot) no. 5580-1/19 sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan 1/3 duty general-purpose lcd display drivers lc75833e, 75833w, 75833je overview the lc75833e, lc75833w, and LC75833JE are 1/3-duty general-purpose lcd display drivers that can be used for frequency display in electronic tuners under the control of a microcontroller. the lc75833e and lc75833w can drive an lcd with up to 105 segments directly, the LC75833JE can drive an lcd with up to 93 segments directly. the lc75833e and lc75833w and LC75833JE can also control up to 8 general-purpose output ports. since the lc75833e, lc75833w, and LC75833JE use separate power supply systems for the lcd drive block and the logic block, the lcd driver block power-supply voltage can be set to any voltage in the range 2.7 to 6.0 volts, regardless of the logic block power-supply voltage. features ? supports both 1/3 duty 1/2 bias and 1/3 duty 1/3 bias lcd drive under serial data control. lc75833e, lc75833w: up to 105 segments LC75833JE: up to 93 segments (without the s12, s23, s24, s35 segment output pins from the lc75833e, lc75833w) ? serial data input supports ccb format communication with the system controller. ? serial data control of the power-saving mode based backup function and all the segments forced off function ? serial data control of switching between the segment output port and the general-purpose output port functions ? high generality, since display data is displayed directly without decoder intervention. ? independent v lcd for the lcd driver block (v lcd can be set to any voltage in the range 2.7 to 6.0 volts, regardless of the logic block power-supply voltage.) ? the inh pin can force the display to the off state. ? rc oscillator circuit package dimensions unit: mm 3156-qfp48e unit: mm 3163a-sqfp48 unit: mm 3148-qfp44ma ? ccb is a trademark of sanyo electric co., ltd. ? ccb is sanyos original bus format and all the bus addresses are controlled by sanyo. [lc75833w] [lc75833e] sanyo: qfp48e [LC75833JE] sanyo: sqfp48 sanyo: qip44ma
specifications absolute maximum ratings at t a = 25 c, v ss = 0 v note: the LC75833JE does not have the s12, s23, s24, s35 output pins. allowable operating ranges at t a = C40 to +85 c, v ss = 0 v no. 5580- 2 /19 lc75833e, 75833w, 75833je parameter symbol conditions ratings unit maximum supply voltage v dd max v dd C0.3 to +7.0 v v lcd max v lcd C0.3 to +7.0 v v in 1 ce, cl, di, inh C0.3 to +7.0 v input voltage v in 2 osc C0.3 to v dd + 0.3 v v in 3 v lcd 1, v lcd 2 C0.3 to v lcd + 0.3 v output voltage v out 1 osc C0.3 to v dd + 0.3 v v out 2 s1 to s35, com1 to com3, p1 to p8 C0.3 to v lcd + 0.3 v i out 1 s1 to s35 300 a output current i out 2 com1 to com3 3 ma i out 3 p1 to p8 5 ma allowable power dissipation pd max ta = 85 c 150 mw operating temperature topr C40 to +85 c storage temperature tstg C55 to +125 c parameter symbol conditions ratings unit min typ max supply voltage v dd v dd 2.7 6.0 v v lcd v lcd 2.7 6.0 v input voltage v lcd 1 v lcd 1 2/3 v lcd v lcd v v lcd 2 v lcd 2 1/3 v lcd v lcd v input high-level voltage v ih ce, cl, di, inh 0.8 v dd 6.0 v input low-level voltage v il ce, cl, di, inh 0 0.2 v dd v recommended external resistance r osc osc 39 k recommended external capacitance c osc osc 1000 pf guaranteed oscillation range f osc osc 19 38 76 khz data setup time t ds cl, di: figure 2 160 ns data hold time t dh cl, di: figure 2 160 ns ce wait time t cp ce, cl: figure 2 160 ns ce setup time t cs ce, cl: figure 2 160 ns ce hold time t ch ce, cl: figure 2 160 ns high-level clock pulse width t ?h cl: figure 2 160 ns low-level clock pulse width t ?l cl: figure 2 160 ns rise time t r ce, cl, di: figure 2 160 ns fall time t f ce, cl, di: figure 2 160 ns inh switching time t c inh, ce: figure 3 10 s
no. 5580- 3 /19 lc75833e, 75833w, 75833je electrical characteristics for the allowable operating ranges note: * 1 excluding the bias voltage generation divider resistors built in the v lcd 1 and v lcd 2. (see figure 1.) the LC75833JE does not have the s12, s23, s24, s35 output pins. parameter symbol conditions ratings unit min typ max hysteresis width v h ce, cl, di, inh 0.1 v dd v input high level current i ih ce, cl, di, inh; v i = 6.0 v 5.0 a input low level current i il ce, cl, di, inh; v i = 0 v C5.0 a v oh 1 s1 to s35; i o = C20 a v lcd C 0.9 v output high-level voltage v oh 2 com1 to com3; i o = C100 a v lcd C 0.9 v v oh 3 p1 to p8; i o = C1 ma v lcd C 0.9 v v ol 1 s1 to s35; i o = 20 a 0.9 v output low-level voltage v ol 2 com1 to com3; i o = 100 a 0.9 v v ol 3 p1 to p8; i o = 1 ma 0.9 v v mid 1 com1 to com3; 1/2 bias, 1/2 v lcd C 0.9 1/2 v lcd + 0.9 v i o = 100 a v mid 2 s1 to s35; 1/3 bias, 2/3 v lcd C 0.9 2/3 v lcd + 0.9 v i o = 20 a output middle-level voltage * 1 v mid 3 s1 to s35; 1/3 bias, 1/3 v lcd C 0.9 1/3 v lcd + 0.9 v i o = 20 a v mid 4 com1 to com3; 1/3 bias, 2/3 v lcd C 0.9 2/3 v lcd + 0.9 v i o = 100 a v mid 5 com1 to com3; 1/3 bias, 1/3 v lcd C 0.9 1/3 v lcd + 0.9 v i o = 100 a oscillator frequency f osc osc; r osc = 39 k c osc = 1000 pf 30.4 38 45.6 khz i dd 1 v dd ; power saving mode 5 a i dd 2 v dd ; v dd = 6.0 v, output open, fosc = 38 k hz 250 500 a i lcd 1 v lcd ; power saving mode 5 a current drain i lcd 2 v lcd ; v lcd = 6.0 v, output open 100 200 a 1/2 bias, fosc = 38 k hz i lcd 3 v lcd ; v lcd = 6.0 v, output open 60 120 a 1/3 bias, fosc = 38 k hz
2. when cl is stopped at the high level figure 2 no. 5580- 4 /19 lc75833e, 75833w, 75833je v lcd 1 v lcd 2 v lcd v ss a06550 t o the common segments driver except these resistors s t? t? tr tf tds tdh tcp tcs tch v il v ih v ih v ih v il v il 50% cl ce di a06551 v ih t? t? tf tr tds tdh tcp tcs tch v il v ih v ih v il v il 50% cl ce di a06552 figure 1 1. when cl is stopped at the low level
pin assignments block diagram note: the LC75833JE does not have the s12, s23, s24, s35 output pins. no. 5580- 5 /19 lc75833e, 75833w, 75833je com2 37 com3 v dd v lcd v lcd 1 v lcd 2 v ss osc inh ce cl di 48 s24 s23 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 13 24 p1/s1 1 12 p2/s2 p3/s3 p4/s4 p5/s5 p6/s6 p7/s7 p8/s8 s9 s10 s11 s12 s25 25 36 s26 s27 s28 s29 s30 s31 s32 s33 s34 s35 com1 lc75833e lc75833w a06549 34 com3 v dd v lcd v lcd 1 v lcd 2 v ss osc inh ce cl di 44 s25 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 12 22 p1/s1 1 11 p2/s2 p3/s3 p4/s4 p5/s5 p6/s6 p7/s7 p8/s8 s9 s10 s11 23 33 s26 s27 s28 s29 s30 s31 s32 s33 s34 com1 com2 LC75833JE a06582 common driver address detector clock generator segment driver & latch shift register inh osc v dd v lcd v lcd 1 v lcd 2 v ss di cl ce com3 com2 com1 s35 s34 s9 s8/p8 s2/p2 s1/p1 a06553
pin functions note: the LC75833JE does not have the s12, s23, s24, s35 output pins. no. 5580- 6 /19 lc75833e, 75833w, 75833je ce: chip enable cl: synchronization clock di: transfer data h s1/p1 to s8/p8 s9 to s35 pin 1 to 8 9 to 35 lc75833e, 75833w LC75833JE 1 to 8 9 to 31 o open segment outputs for displaying the display data transferred by serial data input. the pins s1/p1 to s8/p8 can be used as general-purpose output ports when so set up by the control data. com1 com2 com3 36 37 38 32 33 34 o open common driver outputs. the frame frequency f o is given by: f o = (f osc /384) hz. osc 44 40 ce cl di 46 47 48 42 43 44 serial data transfer inputs. these pins are connected to the control microprocessor. i/o v dd i gnd oscillator connection an oscillator circuit is formed by connecting an external resistor and capacitor to this pin. v lcd 1 41 37 i open used to apply the lcd drive 2/3-bias voltage externally. this pin must be connected to v lcd 2 when 1/2-bias drive is used. v lcd 2 42 38 i open used to apply the lcd drive 1/3-bias voltage externally. this pin must be connected to v lcd 1 when 1/2-bias drive is used. v dd 39 35 logic block power supply. provide a voltage in the range 2.7 to 6.0 v. v lcd 40 36 lcd driver block power supply. provide a voltage in the range 2.7 to 6.0 v. v ss 43 39 ground pin. connect to ground. inh 45 41 l i gnd display off control input ? inh = low (v ss ): off s1/p1 to s8/p8 = low (these pins are forcibly set to the segment output port function and fixed at the v ss level.) s9 to s35 = low (v ss ), com1 to com3 = low (v ss ) ? inh = high (v dd ): on note that serial data transfers can be performed when the display is forced off by this pin. active i/o handling when unused functions pin no.
serial data t ransfer format 1. when cl is stopped at the low level note: dd ... direction data no. 5580- 7 /19 lc75833e, 75833w, 75833je d32 d3 d2 d1 0 1 0 0 0 1 1 0 a3 a2 a1 a0 b3 b2 b1 b0 d33 d34 d35 d36 0 0 0 p0 p1 p2 p3 dr sc bu 0 0 ccb address 8 bits display data 36 bits control data 10 bits dd 2 bits ce cl di d68 d39 d38 d37 0 1 0 0 0 1 1 0 a3 a2 a1 a0 b3 b2 b1 b0 d69 d70 d71 d72 0 0 0 0 0 0 0 0 0 0 0 1 ccb address 8 bits display data 36 bits fixed data 10 bits dd 2 bits d104 d75 d74 d73 0 1 0 0 0 1 1 0 a3 a2 a1 a0 b3 b2 b1 b0 d105 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ccb address 8 bits display data 33 bits fixed data 13 bits dd 2 bits a06554
2. when cl is stopped at the high level note: dd ... direction data ? ccb address ............... 46h ? d1 to d105 ................. display data (at the LC75833JE, the display data d34 to d36, d67 to d72, d103 to d105 must be set to 0. ? p0 to p3 ...................... segment output port/general-purpose output port switching control data ? dr .............................. 1/2-bias drive or 1/3-bias drive switching control data ? sc ............................... segments on/off control data ? bu .............................. normal mode/power-saving mode control data no. 5580- 8 /19 lc75833e, 75833w, 75833je d32 d3 d2 d1 0 1 0 0 0 1 1 0 a3 a2 a1 a0 b3 b2 b1 b0 d33 d34 d35 d36 0 0 0 p0 p1 p2 p3 dr sc bu 0 0 ccb address 8 bits display data 36 bits control data 10 bits dd 2 bits ce cl di d68 d39 d38 d37 0 1 0 0 0 1 1 0 a3 a2 a1 a0 b3 b2 b1 b0 d69 d70 d71 d72 0 0 0 0 0 0 0 0 0 0 0 1 ccb address 8 bits display data 36 bits fixed data 10 bits dd 2 bits d104 d75 d74 d73 0 1 0 0 0 1 1 0 a3 a2 a1 a0 b3 b2 b1 b0 d105 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ccb address 8 bits display data 33 bits fixed data 13 bits dd 2 bits a06555
serial data t ransfer examples ? at the lc75833e and lc75833w when 73 or more segments are used, at the LC75833JE when 64 or more segments are used. 144 bits of serial data must be sent. note: at the LC75833JE, the display data d34 to d36, d67 to d72, d103 to d105 must be set to 0. ? at the lc75833e and lc75833w when used with less than 73 segments, at the LC75833JE when used with less than 64 segments. transfer either 48 bits or 96 bits of serial data depending on the number of segments used. however, the serial data shown in the figure below (the display data d1 to d36 and the control data) must be sent. note: at the LC75833JE, the display data d34 to d36 must be set to 0. control data functions 1. p0 to p3: segment output port/general-purpose output port switching control data. these control data bits switch the s1/p1 to s8/p8 output pins between their segment output port and general-purpose output port functions. note: sn (n = 1 to 8): segment output ports pn (n = 1 to 8): general-purpose output ports no. 5580- 9 /19 lc75833e, 75833w, 75833je control data output pin states p0 p1 p2 p3 s1/p1 s2/p2 s3/p3 s4/p4 s5/p5 s6/p6 s7/p7 s8/p8 0 0 0 0 s1 s2 s3 s4 s5 s6 s7 s8 0 0 0 1 p1 s2 s3 s4 s5 s6 s7 s8 0 0 1 0 p1 p2 s3 s4 s5 s6 s7 s8 0 0 1 1 p1 p2 p3 s4 s5 s6 s7 s8 0 1 0 0 p1 p2 p3 p4 s5 s6 s7 s8 0 1 0 1 p1 p2 p3 p4 p5 s6 s7 s8 0 1 1 0 p1 p2 p3 p4 p5 p6 s7 s8 0 1 1 1 p1 p2 p3 p4 p5 p6 p7 s8 1 0 0 0 p1 p2 p3 p4 p5 p6 p7 p8 d1 d2 d3 d31 d32 d33 0 1 1 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d34 d35 d36 0 0 0 p0 p1 p2 p3 dr sc bu 0 0 8 bits 48 bits d37 d38 d39 d67 d68 d69 0 1 1 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d70 d71 d72 0 0 0 0 0 0 0 0 0 0 0 1 d73 d74 d75 d103 d104 d105 0 1 1 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 a06556 d1 d2 d3 d31 d32 d33 0 1 1 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d34 d35 d36 0 0 0 p0 p1 p2 p3 dr sc bu 0 0 8 bits 48 bits a06557
also note that when the general-purpose output port function is selected, the output pins and the display data will have the correspondences listed in the tables below. for example, if the output pin s4/p4 has the general-purpose output port function selected, it will output a high level (v lcd ) when the display data d10 is 1, and will output a low level (v ss ) when d10 is 0. 2. dr: 1/2-bias drive or 1/3-bias drive switching control data this control data bit selects either 1/2-bias drive or 1/3-bias drive. 3. sc: segments on/off control data this control data bit controls the on/off state of the segments. however, note that when the segments are turned off by setting sc to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. 4. bu: normal mode/power-saving mode control data this control data bit selects either normal mode or power-saving mode. no. 5580- 10 /19 lc75833e, 75833w, 75833je dr drive type 0 1/3-bias drive 1 1/2-bias drive sc display state 0 on 1 off bu mode 0 normal mode power saving mode (the osc pin oscillator is stopped, and the common and segment output pins go to the vss level. however, the 1 s1/p1 to s8/p8 output pins that are set to be general-purpose output ports by the control data p0 to p3 can be used as general- purpose output ports.) output pin corresponding display data s1/p1 d1 s2/p2 d4 s3/p3 d7 s4/p4 d10 output pin corresponding display data s5/p5 d13 s6/p6 d16 s7/p7 d19 s8/p8 d22
display data to segment output pin correspondence note: this applies to the case where the s1/p1 to s8/p8 output pins are set to be segment output ports. the LC75833JE do not have the s12, s23, s24, s35 output pins. for example, the table below lists the segment output states for the s11 output pin. no. 5580- 11 /19 lc75833e, 75833w, 75833je segment com1 com2 com3 output pin s1/p1 d1 d2 d3 s2/p2 d4 d5 d6 s3/p3 d7 d8 d9 s4/p4 d10 d11 d12 s5/p5 d13 d14 d15 s6/p6 d16 d17 d18 s7/p7 d19 d20 d21 s8/p8 d22 d23 d24 s9 d25 d26 d27 s10 d28 d29 d30 s11 d31 d32 d33 s12 d34 d35 d36 s13 d37 d38 d39 s14 d40 d41 d42 s15 d43 d44 d45 s16 d46 d47 d48 s17 d49 d50 d51 s18 d52 d53 d54 segment com1 com2 com3 output pin s19 d55 d56 d57 s20 d58 d59 d60 s21 d61 d62 d63 s22 d64 d65 d66 s23 d67 d68 d69 s24 d70 d71 d72 s25 d73 d74 d75 s26 d76 d77 d78 s27 d79 d80 d81 s28 d82 d83 d84 s29 d85 d86 d87 s30 d88 d89 d90 s31 d91 d92 d93 s32 d94 d95 d96 s33 d97 d98 d99 s34 d100 d101 d102 s35 d103 d104 d105 display data segment output pin (s11) state d31 d32 d33 0 0 0 the lcd segments corresponding to com1 to com3 are off. 0 0 1 the lcd segments corresponding to com3 is on. 0 1 0 the lcd segments corresponding to com2 is on. 0 1 1 the lcd segments corresponding to com2 and com3 are on. 1 0 0 the lcd segments corresponding to com1 is on. 1 0 1 the lcd segments corresponding to com1 and com3 are on. 1 1 0 the lcd segments corresponding to com1 and com2 are on. 1 1 1 the lcd segments corresponding to com1 to com3 are on.
1/3-duty 1/2-bias drive t echnique no. 5580- 12 /19 lc75833e, 75833w, 75833je 1/3-duty 1/2-bias waveforms fosc 384 [hz] com1 v lcd v lcd1 , v lcd2 0 v v lcd v lcd1 , v lcd2 0 v v lcd v lcd1 , v lcd2 0 v v lcd v lcd1 , v lcd2 0 v v lcd v lcd1 , v lcd2 0 v v lcd v lcd1 , v lcd2 0 v v lcd v lcd1 , v lcd2 0 v v lcd v lcd1 , v lcd2 0 v v lcd v lcd1 , v lcd2 0 v v lcd v lcd1 , v lcd2 0 v v lcd v lcd1 , v lcd2 0 v com2 com3 a06558 lcd driver output when all lcd segments corresponding to com1, com2, and com3 are turned off. lcd driver output when only lcd segments corresponding to com1 are on (lit). lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when all lcd segments corresponding to com1, com2, and com3 are on.
fosc 384 [hz] com1 v lcd v lcd1 v lcd2 0 v v lcd v lcd1 v lcd2 0 v v lcd v lcd1 v lcd2 0 v v lcd v lcd1 v lcd2 0 v v lcd v lcd1 v lcd2 0 v v lcd v lcd1 v lcd2 0 v v lcd v lcd1 v lcd2 0 v v lcd v lcd1 v lcd2 0 v v lcd v lcd1 v lcd2 0 v v lcd v lcd1 v lcd2 0 v v lcd v lcd1 v lcd2 0 v com2 com3 1/3-duty 1/3-bias t echnique no. 5580- 13 /19 lc75833e, 75833w, 75833je lcd driver output when all lcd segments corresponding to com1, com2, and com3 are turned off. lcd driver output when only lcd segments corresponding to com1 are on (lit). lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when all lcd segments corresponding to com1, com2, and com3 are on. 1/3-duty 1/3-bias waveforms a06559
the inh pin and display control since the lsi internal data (the display data and the control data) is undefined when power is first applied, applications should set the inh pin low at the same time as power is applied to turn off the display (lc75833e, lc75833w: this sets the s1/p1 to s8/p8, s9 to s35, and com1 to com3 to the v ss level. LC75833JE: this sets the s1/p1 to s8/p8, s9 to s11, s13 to s22, s25 to s34, and com1 to com3 to the v ss level.) and during this period send serial data from the controller. the controller should then set the inh pin high after the data transfer has completed. this procedure prevents meaningless displays at power on. (see f igure 3.) notes on the power on/off sequences applications should observe the following sequence when turning the lc75833e, lc75833w, and LC75833JE power on and off. ? at power on: logic block power supply (v dd ) on ? lcd driver block power supply (v lcd ) on ? at power off: lcd driver block power supply (v lcd ) off ? logic block power supply (v dd ) off however, if the logic and lcd driver block use a shared power supply, then the power supplies can be turned on and off at the same time. figure 3 notes on controller t ransfer of display data since the lc75833e, lc75833w, and LC75833JE accept display data divided into three separate transfer operations, we recommend that applications transfer all of the display data within a period of less than 30 ms to prevent observable degradation of display quality. no. 5580- 14 /19 lc75833e, 75833w, 75833je v dd v lcd inh ce d1 to d36 p0 to p3 internal data internal data internal data dr, sc, bu (d37 to d72) (d73 to d105) t 1 t 2 t 3 v il tc v il display and control data transfer undefined undefined undefined defined defined defined undefined undefined undefined a 0 6 5 6 0 note: at the LC75833JE, the display data d34 to d36, d67 to d72, d103 to d105 must be set to 0. note: t1 3 0 t2 > 0 t3 3 0 (t2 > t3) tc ... 10 s min
sample application circuit 1 1/2 bias (for use with normal size panels) ? lc75833e, lc75833w note: * 2 when a capacitor except the recommended external capacitance (c osc = 1000 pf) is connected the osc pin, we recommend that applications connect the osc pin with a capacitor in the range 220 to 2200pf. ? LC75833JE note: * 2 when a capacitor except the recommended external capacitance (c osc = 1000 pf) is connected the osc pin, we recommend that applications connect the osc pin with a capacitor in the range 220 to 2200pf. no. 5580- 15 /19 lc75833e, 75833w, 75833je v dd v ss v lcd v lcd1 v lcd2 inh ce cl di com1 com2 com3 p1/s1 p2/s2 p8/s8 s9 s33 s34 s35 +3 v +5 v c 3 0.047 f from the controller osc * 2 (p1) (p2) (p8) general-purpose output ports used for functions such as backlight control a 0 6 5 6 1 lcd panel (up to 105 segments) c v dd v ss v lcd v lcd1 v lcd2 inh ce cl di com1 com2 com3 p1/s1 p2/s2 p8/s8 s9 s10 s11 s13 s22 s25 s34 +3 v +5 v from the controller osc * 2 (p1) (p2) (p8) general-purpose output ports used for functions such as backlight control lcd panel (up to 93 segments) a 0 6 5 8 3 c 3 0.047 f c
sample application circuit 2 1/2 bias (for use with large panels) ? lc75833e, lc75833w note: * 2 when a capacitor except the recommended external capacitance (c osc = 1000 pf) is connected the osc pin, we recommend that applications connect the osc pin with a capacitor in the range 220 to 2200pf. ? LC75833JE note: * 2 when a capacitor except the recommended external capacitance (c osc = 1000 pf) is connected the osc pin, we recommend that applications connect the osc pin with a capacitor in the range 220 to 2200pf. no. 5580- 16 /19 lc75833e, 75833w, 75833je v dd v ss v lcd v lcd1 v lcd2 inh ce cl di com1 com2 com3 p1/s1 p2/s2 p8/s8 s9 s33 s34 s35 +3 v +5 v from the controller osc * 2 (p1) (p2) (p8) general-purpose output ports used for functions such as backlight control a 0 6 5 6 2 lcd panel (up to 105 segments) c 3 0.047 f 10k 3 r 3 1k c r r v dd v ss v lcd v lcd1 v lcd2 inh ce cl di com1 com2 com3 p1/s1 p2/s2 p8/s8 s9 s10 s11 s13 s22 s25 s34 osc * 2 (p1) (p2) (p8) general-purpose output ports used for functions such as backlight control a 0 6 5 8 4 +3 v +5 v from the controller lcd panel (up to 93 segments) c 3 0.047 f 10k 3 r 3 1k c r r
sample application circuit 3 1/3 bias (for use with normal size panels) ? lc75833e, lc75833w note: * 2 when a capacitor except the recommended external capacitance (c osc = 1000 pf) is connected the osc pin, we recommend that applications connect the osc pin with a capacitor in the range 220 to 2200pf. ? LC75833JE note: * 2 when a capacitor except the recommended external capacitance (c osc = 1000 pf) is connected the osc pin, we recommend that applications connect the osc pin with a capacitor in the range 220 to 2200pf. no. 4801- 17 /19 lc75833e, 75833w, 75833je v dd v ss v lcd v lcd1 v lcd2 inh ce cl di com1 com2 com3 p1/s1 p2/s2 p8/s8 s9 s33 s34 s35 +3 v +5 v c 3 0.047 f from the controller osc * 2 (p1) (p2) (p8) general-purpose output ports used for functions such as backlight control a 0 6 5 6 2 c c lcd panel (up to 105 segments) v dd v ss v lcd v lcd1 v lcd2 inh ce cl di com1 com2 com3 p1/s1 p2/s2 p8/s8 s9 s10 s11 s13 s22 s25 s34 osc * 2 (p1) (p2) (p8) general-purpose output ports used for functions such as backlight control a 0 6 5 8 4 +3 v +5 v c 3 0.047 f from the controller c c lcd panel (up to 93 segments)
sample application circuit 4 1/3 bias (for use with large panels) ? lc75833e, lc75833w note: * 2 when a capacitor except the recommended external capacitance (c osc = 1000 pf) is connected the osc pin, we recommend that applications connect the osc pin with a capacitor in the range 220 to 2200pf. no. 5580- 18 /19 lc75833e, 75833w, 75833je v dd v ss v lcd v lcd1 v lcd2 inh ce cl di com1 com2 com3 p1/s1 p2/s2 p8/s8 s9 s33 s34 s35 osc * 2 (p1) (p2) (p8) general-purpose output ports used for functions such as backlight control a 0 6 5 6 3 lcd panel (up to 105 segments) +3 v +5 v from the controller c 3 0.047 f 10 k 3 r 3 1 k c c r r r
ps no. 5580-19/19 lc75833e, 75833w, 75833je ? LC75833JE note: * 2 when a capacitor except the recommended external capacitance (c osc = 1000 pf) is connected the osc pin, we recommend that applications connect the osc pin with a capacitor in the range 220 to 2200pf. this catalog provides information as of march 1998. specifications and information herein are subject to change without notice. n no products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n anyone purchasing any products described or contained herein for an above-mentioned use shall: ? accept full responsibility and indemnify and defend sanyo electric co., ltd., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on sanyo electric co., ltd., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. v dd v ss v lcd v lcd1 v lcd2 inh ce cl di com1 com2 com3 p1/s1 p2/s2 p8/s8 s9 s10 s11 s13 s22 s25 s34 +3 v +5 v from the controller osc * 2 (p1) (p2) (p8) general-purpose output ports used for functions such as backlight control lcd panel (up to 93 segments) a 0 6 5 8 5 c 3 0.047 f 10 k 3 r 3 1 k c c r r r

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